repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
0intro/plan9 | 2,282 | sys/src/libc/sparc/memmove.s | TEXT memmove(SB), $0
JMP move
TEXT memcpy(SB), $0
move:
/*
* performance:
* (tba)
*/
MOVW R7, s1+0(FP)
MOVW n+8(FP), R9 /* R9 is count */
MOVW R7, R10 /* R10 is to-pointer */
SUBCC R0,R9, R0
BGE ok
MOVW 0(R0), R0
ok:
MOVW s2+4(FP), R11 /* R11 is from-pointer */
ADD R9,R11, R13 /* R13 is end from-... |
0intro/plan9 | 1,705 | sys/src/libc/sparc/memcmp.s | TEXT memcmp(SB), $0
/*
* performance:
* (tba)
*/
MOVW R7, 0(FP)
MOVW n+8(FP), R9 /* R9 is count */
MOVW s1+0(FP), R10 /* R10 is pointer1 */
MOVW s2+4(FP), R11 /* R11 is pointer2 */
ADD R9,R10, R12 /* R12 is end pointer1 */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to guarantee ... |
0intro/plan9 | 1,115 | sys/src/libc/sparc/strcpy.s | TEXT strcpy(SB), $0
MOVW R7, 0(FP)
MOVW s1+0(FP), R9 /* R9 is to pointer */
MOVW s2+4(FP), R10 /* R10 is from pointer */
/*
* test if both pointers
* are similarly word aligned
*/
XOR R9,R10, R7
ANDCC $3,R7, R0
BNE una
/*
* make byte masks
*/
MOVW $0xff, R17
SLL $8,R17, R16
SLL $16,R17, R13
SLL $24,... |
0intro/plan9 | 5,379 | sys/src/libc/sparc/muldivrt.s | /*
* ulong
* _udiv(ulong num, ulong den)
* {
* int i;
* ulong quo;
*
* if(den == 0)
* *(ulong*)-1 = 0;
* quo = num;
* if(quo > 1<<(32-1))
* quo = 1<<(32-1);
* for(i=0; den<quo; i++)
* den <<= 1;
* quo = 0;
* for(; i>=0; i--) {
* quo <<= 1;
* if(num >= den) {
* num -= den;
* qu... |
0intro/plan9 | 2,423 | sys/src/libc/sparc/vlop.s | TEXT _mulv(SB), $0
MOVW u1+8(FP), R8
MOVW u2+16(FP), R13
MOVW R13, R16 /* save low parts for later */
MOVW R8, R12
/*
* unsigned 32x32 => 64 multiply
*/
CMP R13, R8
BLE mul1
MOVW R12, R13
MOVW R16, R8
mul1:
MOVW R13, Y
ANDNCC $0xFFF, R13, R0
BE mul_shortway
ANDCC R0, R0, R9 /* zero partial product ... |
0intro/plan9 | 1,282 | sys/src/libc/arm/atom.s | #define CLREX WORD $0xf57ff01f
#define LDREX(a,r) WORD $(0xe<<28|0x01900f9f | (a)<<16 | (r)<<12)
/* `The order of operands is from left to right in dataflow order' - asm man */
#define STREX(v,a,r) WORD $(0xe<<28|0x01800f90 | (a)<<16 | (r)<<12 | (v)<<0)
/*
* int cas(ulong *p, ulong ov, ulong nv);
*/
TEXT cas+0(SB)... |
0intro/plan9 | 4,196 | sys/src/libc/arm/memmove.s | TS = 0
TE = 1
FROM = 2
N = 3
TMP = 3 /* N and TMP don't overlap */
TMP1 = 4
TEXT memcpy(SB), $0
B _memmove
TEXT memmove(SB), $0
_memmove:
MOVW R(TS), to+0(FP) /* need to save for return value */
MOVW from+4(FP), R(FROM)
MOVW n+8(FP), R(N)
ADD R(N), R(TS), R(TE) /* to end pointer */
CMP R(FROM), R(TS)
BLS... |
0intro/plan9 | 1,639 | sys/src/libc/arm/div.s | Q = 0
N = 1
D = 2
CC = 3
TMP = 11
TEXT save<>(SB), 1, $0
MOVW R(Q), 0(FP)
MOVW R(N), 4(FP)
MOVW R(D), 8(FP)
MOVW R(CC), 12(FP)
MOVW R(TMP), R(Q) /* numerator */
MOVW 20(FP), R(D) /* denominator */
CMP $0, R(D)
BNE s1
MOVW -1(R(D)), R(TMP) /* divide by zero fault */
s1: RET
TEXT rest<>(SB), 1, $0
MOVW 0(F... |
0intro/plan9 | 1,270 | sys/src/libc/mips/memset.s | TEXT memset(SB),$12
MOVW R1, 0(FP)
/*
* performance:
* about 1us/call and 28mb/sec
*/
MOVW n+8(FP), R3 /* R3 is count */
MOVW p+0(FP), R4 /* R4 is pointer */
MOVW c+4(FP), R5 /* R5 is char */
ADDU R3,R4, R6 /* R6 is end pointer */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to gua... |
0intro/plan9 | 3,481 | sys/src/libc/mips/memmove.s | TEXT memmove(SB), $0
JMP move
TEXT memcpy(SB), $0
move:
MOVW R1, s1+0(FP)
MOVW n+8(FP), R3 /* R3 is count */
MOVW R1, R4 /* R4 is to-pointer */
SGT R0, R3, R5
BEQ R5, ok
MOVW (R0), R0 /* abort if negative count */
ok:
MOVW s2+4(FP), R5 /* R5 is from-pointer */
ADDU R3,R5, R7 /* R7 is end from-pointe... |
0intro/plan9 | 1,682 | sys/src/libc/mips/memcmp.s | TEXT memcmp(SB), $0
MOVW R1, 0(FP)
/*
* performance:
* alligned about 1.0us/call and 17.4mb/sec
* unalligned is about 3.1mb/sec
*/
MOVW n+8(FP), R3 /* R3 is count */
MOVW s1+0(FP), R4 /* R4 is pointer1 */
MOVW s2+4(FP), R5 /* R5 is pointer2 */
ADDU R3,R4, R6 /* R6 is end pointer1 */
/*
* if not at leas... |
0intro/9legacy | 17,538 | sys/src/9/kw/l.s | /*
* sheevaplug machine assist
* arm926ej-s processor at 1.2GHz
*
* loader uses R11 as scratch.
* R9 and R10 are used for `extern register' variables.
*
* ARM v7 arch. ref. man. (I know, this is v5) §B1.3.3 that
* we don't need barriers around moves to CPSR. The ARM v6 manual
* seems to be silent on the subje... |
0intro/plan9 | 1,202 | sys/src/libc/mips/strcpy.s | TEXT strcpy(SB), $0
MOVW s2+4(FP),R2 /* R2 is from pointer */
MOVW R1, R3 /* R3 is to pointer */
/*
* align 'from' pointer
*/
l1:
AND $3, R2, R5
ADDU $1, R2
BEQ R5, l2
MOVB -1(R2), R5
ADDU $1, R3
MOVB R5, -1(R3)
BNE R5, l1
RET
/*
* test if 'to' is also alligned
*/
l2:
AND $3,R3, R5
BEQ R5, l4
/*
... |
0intro/plan9 | 6,371 | sys/src/boot/pc/pbsdebug.s | /*
* Debugging boot sector. Reads the first directory
* sector from disk and displays it.
*
* It relies on the _volid field in the FAT header containing
* the LBA of the root directory.
*/
#include "x16.h"
#define DIROFF 0x00200 /* where to read the root directory (offset) */
#define LOADSEG (0x10000/16) /* ... |
0intro/plan9 | 6,021 | sys/src/boot/pc/pbslbadebug.s | /*
* Debugging boot sector. Reads the first directory
* sector from disk and displays it.
*
* It relies on the _volid field in the FAT header containing
* the LBA of the root directory.
*/
#include "x16.h"
#define DIROFF 0x00200 /* where to read the root directory (offset) */
#define LOADSEG (0x10000/16) /* ... |
0intro/9legacy | 1,298 | sys/src/9/kw/lproc.s | #include "mem.h"
#include "arm.h"
/*
* This is the first jump from kernel to user mode.
* Fake a return from interrupt.
*
* Enter with R0 containing the user stack pointer.
* UTZERO + 0x20 is always the entry point.
*
*/
TEXT touser(SB), 1, $-4
/* store the user stack pointer into the USR_r13 */
MOVM.DB.W... |
0intro/plan9 | 6,530 | sys/src/boot/pc/pbsraw.s | /*
* Partition Boot Sector. Loaded at 0x7C00:
* 8a pbsraw.s; 8l -o pbsraw -l -H3 -T0x7C00 pbsraw.8
* Will load the target at LOADSEG*16+LOADOFF, so the target
* should be probably be loaded with LOADOFF added to the
* -Taddress.
* If LOADSEG is a multiple of 64KB and LOADOFF is 0 then
* targets larger than 64KB... |
0intro/plan9 | 6,217 | sys/src/boot/pc/mbr.s | /*
* Hard disc boot block. Loaded at 0x7C00, relocates to 0x0600:
* 8a mbr.s; 8l -o mbr -l -H3 -T0x0600 mbr.8
*/
#include "x16.h"
/*#define FLOPPY 1 /* test on a floppy */
#define TRACE(C) PUSHA;\
CLR(rBX);\
MOVB $C, AL;\
LBI(0x0E, rAH);\
BIOSCALL(0x10);\
POPA
/*
* We keep data on the stack, index... |
0intro/plan9 | 8,274 | sys/src/boot/pc/pbs.s | /*
* FAT Partition Boot Sector. Loaded at 0x7C00:
* 8a pbs.s; 8l -o pbs -l -H3 -T0x7C00 pbs.8
* Will load the target at LOADSEG*16+LOADOFF, so the target
* should be probably be loaded with LOADOFF added to the
* -Taddress.
* If LOADSEG is a multiple of 64KB and LOADOFF is 0 then
* targets larger than 64KB can b... |
0intro/9legacy | 1,904 | sys/src/9/kw/arm.s | /*
* sheevaplug machine assist, definitions
* arm926ej-s processor at 1.2GHz
*
* loader uses R11 as scratch.
*/
#include "mem.h"
#include "arm.h"
#undef B /* B is for 'botch' */
#define PADDR(a) ((a) & ~KZERO)
#define KADDR(a) (KZERO|(a))
#define L1X(va) (((((va))>>20) & 0x0fff)<<2)
#define MACHADDR (L1-M... |
0intro/plan9 | 8,163 | sys/src/boot/pc/pbslba.s | /*
* FAT Partition Boot Sector. Loaded at 0x7C00:
* 8a pbslba.s; 8l -o pbslba -l -H3 -T0x7C00 pbslba.8
* Will load the target at LOADSEG*16+LOADOFF, so the target
* should be probably be loaded with LOADOFF added to the
* -Taddress.
* If LOADSEG is a multiple of 64KB and LOADOFF is 0 then
* targets larger than 6... |
0intro/9legacy | 5,909 | sys/src/9/kw/lexception.s | /*
* arm exception handlers
*/
#include "arm.s"
#undef B /* B is for 'botch' */
/*
* exception vectors, copied by trapinit() to somewhere useful
*/
TEXT vectors(SB), 1, $-4
MOVW 0x18(R15), R15 /* reset */
MOVW 0x18(R15), R15 /* undefined instr. */
MOVW 0x18(R15), R15 /* SWI & SMC */
MOVW 0x18(R15), R1... |
0intro/plan9 | 5,369 | sys/src/libsec/386/md5block.s | /*
* rfc1321 requires that I include this. The code is new. The constants
* all come from the rfc (hence the copyright). We trade a table for the
* macros in rfc. The total size is a lot less. -- presotto
*
* Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All
* rights reserved.
*
* License t... |
0intro/plan9 | 3,682 | sys/src/libsec/386/sha1block.s | TEXT _sha1block+0(SB),$352
/* x = (wp[off-f] ^ wp[off-8] ^ wp[off-14] ^ wp[off-16]) <<< 1;
* wp[off] = x;
* x += A <<< 5;
* E += 0xca62c1d6 + x;
* x = FN(B,C,D);
* E += x;
* B >>> 2
*/
#define BSWAPDI BYTE $0x0f; BYTE $0xcf;
#define BODY(off,FN,V,A,B,C,D,E)\
MOVL (off-64)(BP),DI;\
XORL (off-56)(BP),DI;\
XO... |
0intro/9legacy | 4,052 | sys/src/9/kw/rebootcode.s | /*
* sheevaplug reboot code
*
* R11 is used by the loader as a temporary, so avoid it.
*/
#include "arm.s"
/*
* Turn off MMU, then copy the new kernel to its correct location
* in physical memory. Then jump to the start of the kernel.
*/
/* main(PADDR(entry), PADDR(code), size); */
TEXT main(SB), 1, $-4
MOVW... |
0intro/plan9 | 7,204 | sys/src/libsec/mips/md5block.s | /*
* rfc1321 requires that I include this. The code is new. The constants
* all come from the rfc (hence the copyright). We trade a table for the
* macros in rfc. The total size is a lot less. -- presotto
*
* Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All
* rights reserved.
*
* License t... |
0intro/plan9 | 4,143 | sys/src/libsec/mips/sha1block.s | TEXT _sha1block+0(SB),$328
/*
* wp[off] = x;
* x += A <<< 5;
* E += 0xca62c1d6 + x;
* x = FN(B,C,D);
* E += x;
* B >>> 2
*/
#define BODYX(off,FN,V,A,B,C,D,E)\
FN(B,C,D)\
ADDU TMP1,E;\
ADDU V,E;\
MOVW TMP2,off(WREG);\
ADDU TMP2,E;\
SLL $5,A,TMP3;\
SRL $27,A,TMP4;\
OR TMP3,TMP4;\
ADDU TMP4,E;\
SLL $30,... |
0intro/plan9 | 1,233 | sys/src/libmp/power/mpvecadd.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
/*
* mpvecadd(mpdigit *a, int alen, mpdigit *b, int blen, mpdigit *sum)
*
* sum[0:alen] = a[0:alen-1] + b[0:blen-1]
*
* prereq: alen >= blen, sum has room for alen+1 digits
*
* R3 == a (first arg passed in R3)
* R4 == alen
* R5 == b
* R6 == blen
* R7 == sum
... |
0intro/plan9 | 1,118 | sys/src/libmp/power/mpvecsub.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
/*
* mpvecsub(mpdigit *a, int alen, mpdigit *b, int blen, mpdigit *diff)
*
* diff[0:alen-1] = a[0:alen-1] - b[0:blen-1]
*
* prereq: alen >= blen, diff has room for alen digits
*
* R3 == a
* R4 == alen
* R5 == b
* R6 == blen
* R7 == diff
* R8 == temporary
*... |
0intro/plan9 | 1,300 | sys/src/libmp/power/mpvecdigmulsub.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
#define BLT BC 0xC,0,
/*
* mpvecdigmulsub(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p -= b*m
*
* each step looks like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* b = R3
* n = R4
* m = R5
... |
0intro/plan9 | 1,105 | sys/src/libmp/power/mpvecdigmuladd.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
/*
* mpvecdigmuladd(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p += b*m
*
* each step looks like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* b = R3
* n = R4
* m = R5
* p = R6
* i = R7
... |
0intro/plan9 | 1,063 | sys/src/libmp/386/mpvecdigmuladd.s | /*
* mpvecdigmul(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p += b*m
*
* each step look like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* hi = DX - constrained by hardware
* lo = AX - constrained by hardware
* b+n = SI - can't be BP... |
0intro/plan9 | 1,211 | sys/src/libmp/mips/mpvecadd.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
/*
* mpvecadd(mpdigit *a, int alen, mpdigit *b, int blen, mpdigit *sum)
*
* sum[0:alen] = a[0:alen-1] + b[0:blen-1]
*
* prereq: alen >= blen, sum has room for alen+1 digits
*
* R1 == a (first arg passed in R1)
* R3 == carry
* R4 == alen
* R5 == b
* R6 == blen... |
0intro/plan9 | 1,209 | sys/src/libmp/mips/mpvecsub.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
/*
* mpvecadd(mpdigit *a, int alen, mpdigit *b, int blen, mpdigit *sum)
*
* sum[0:alen] = a[0:alen-1] - b[0:blen-1]
*
* prereq: alen >= blen, sum has room for alen+1 digits
*
* R1 == a (first arg passed in R1)
* R3 == carry
* R4 == alen
* R5 == b
* R6 == blen... |
0intro/plan9 | 1,226 | sys/src/libmp/mips/mpvecdigmulsub.s | /*
* mpvecdigmulsub(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p -= b*m
*
* each step looks like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* b = R1
* n = R4
* m = R5
* p = R6
* i = R7
* hi = R8 - constrained by hardware
* lo... |
0intro/plan9 | 1,098 | sys/src/libmp/mips/mpvecdigmuladd.s | /*
* mpvecdigmuladd(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p += b*m
*
* each step looks like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* b = R1
* n = R4
* m = R5
* p = R6
* i = R7
* hi = R8 - constrained by hardware
* lo... |
0intro/9legacy | 19,997 | sys/src/9/vt4/l.s | /* virtex4 ppc405 machine assist */
#include "mem.h"
/*
* 405 Special Purpose Registers of interest here
*/
#define SPR_CCR0 947 /* Core Configuration Register 0 */
#define SPR_DAC1 1014 /* Data Address Compare 1 */
#define SPR_DAC2 1015 /* Data Address Compare 2 */
#define SPR_DBCR0 1010 /* Debug Control Regist... |
0intro/9legacy | 1,930 | sys/src/9/vt4/tlb.s | /* virtex4 ppc405 initial tlbs */
#include "mem.h"
#define MB (1024*1024)
/*
* TLB prototype entries, loaded once-for-all at startup,
* remaining unchanged thereafter.
* Limit the table size to ensure it fits in small TLBs.
*/
#define TLBE(hi, lo) WORD $(hi); WORD $(lo)
/*
* WARNING: applying TLBG to instructio... |
0intro/9legacy | 3,385 | sys/src/9/vt4/rebootcode.s | /* virtex4 ppc405 reboot code */
#include "mem.h"
#define SPR_SRR0 26 /* Save/Restore Register 0 */
#define SPR_SRR1 27 /* Save/Restore Register 1 */
#define SPR_DCWR 954 /* Data Cache Write-through Register */
#define SPR_DCCR 1018 /* Data Cache Cachability Register */
#define SPR_ICCR 1019 /* Instruction Cache ... |
0intro/9legacy | 21,041 | sys/src/9/loongson64/l.s | #include "mem.h"
#include "spim64.s"
/*
* entrypoint. set SB, pass arguments to main().
* PMON's calling convention:
* argc R4
* argv R5
* envp R6
* callvec R7
*/
TEXT start(SB), $-8
MOVV $setR30(SB), R30
PUTC('9', R1, R2)
/* don't enable any interrupts, out of EXL mode */
MOVW $(CU1|KX|UX), R1
MOVW... |
0intro/9legacy | 2,024 | sys/src/9/loongson64/spim64.s | #undef MASK
#define MASK(w) ((1ull<<(w))-1)
#define NOP NOR R0, R0, R0
#define CONST(x,r) MOVW $((x)&0xffff0000), r; OR $((x)&0xffff), r
#define LL(base, rt) WORD $((060<<26)|((base)<<21)|((rt)<<16))
#define SC(base, rt) WORD $((070<<26)|((base)<<21)|((rt)<<16))
#define ERET WORD $0x42000018; NOP
#define SYNC WOR... |
0intro/9legacy | 21,476 | sys/src/9/rb/l.s | /*
* mips 24k machine assist for routerboard rb450g
*/
#include "mem.h"
#include "mips.s"
#define SANITY 0x12345678
NOSCHED
/*
* Boot only processor
*/
TEXT start(SB), $-4
/* save parameters passed from routerboot */
MOVW R4, R19 /* argc */
MOVW R5, R20 /* argv */
MOVW R6, R21 /* envp */
MOVW R7, R23... |
0intro/9legacy | 1,288 | sys/src/9/rb/initreboot.s | /*
* mips 24k machine assist for routerboard rb450g (minimal for reboot)
*/
#include "mem.h"
#include "mips.s"
NOSCHED
TEXT _main(SB), $0
MOVW $setR30(SB), R30
JMP main(SB)
NOP
/* target for JALRHB in BARRIERS */
TEXT ret(SB), $-4
JMP (R22)
NOP
TEXT setsp(SB), $-4
MOVW R1, SP
RETURN
TEXT coherence(SB... |
0intro/9legacy | 2,331 | sys/src/9/rb/mips.s | /*
* mips 24k machine assist
*/
#undef MASK
#define MASK(w) ((1<<(w))-1)
#define SP R29
#define NOP NOR R0, R0, R0
/* a SPECIAL2 op-code from MIPS32 */
#define CLZ(rs,rd) WORD $(0x70000020 | (rs)<<21 | (rd)<<16 | (rd)<<11)
#define CONST(x,r) MOVW $((x)&0xffff0000), r; OR $((x)&0xffff), r
/* a mips 24k erratum re... |
0intro/9legacy | 18,757 | sys/src/9/teg2/l.s | /*
* tegra 2 SoC machine assist
* dual arm cortex-a9 processors
*
* ARM v7 arch. ref. man. §B1.3.3 says that we don't need barriers
* around writes to CPSR.
*
* LDREX/STREX use an exclusive monitor, which is part of the data cache unit
* for the L1 cache, so they won't work right if the L1 cache is disabled.
*... |
0vercl0k/wtf | 71,203 | src/libs/BLAKE3/c/blake3_sse2_x86-64_windows_gnu.S | .intel_syntax noprefix
.global blake3_hash_many_sse2
.global _blake3_hash_many_sse2
.global blake3_compress_in_place_sse2
.global _blake3_compress_in_place_sse2
.global blake3_compress_xof_sse2
.global _blake3_compress_xof_sse2
.section .text
.p2align 6
_blake3_hash_many_sse2:
blake3_hash_many_sse2:
pu... |
0intro/9legacy | 5,687 | sys/src/9/teg2/cache.v7.s | /*
* cortex arm arch v7 cache flushing and invalidation
* included by l.s and rebootcode.s
*/
TEXT cacheiinv(SB), $-4 /* I invalidate */
MOVW $0, R0
MTCP CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall /* ok on cortex */
ISB
RET
/*
* set/way operators, passed a suitable set/way value in R0.
*/
TEXT ca... |
0vercl0k/wtf | 91,004 | src/libs/BLAKE3/c/blake3_avx512_x86-64_windows_gnu.S | .intel_syntax noprefix
.global _blake3_hash_many_avx512
.global blake3_hash_many_avx512
.global blake3_compress_in_place_avx512
.global _blake3_compress_in_place_avx512
.global blake3_compress_xof_avx512
.global _blake3_compress_xof_avx512
.section .text
.p2align 6
_blake3_hash_many_avx512:
blake3_hash_many_avx512:
... |
0vercl0k/wtf | 61,143 | src/libs/BLAKE3/c/blake3_sse41_x86-64_unix.S | #if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(__ELF__) && defined(__CET__) && defined(__has_include)
#if __has_include(<cet.h>)
#include <cet.h>
#endif
#endif
#if !defined(_CET_ENDBR)
#define _CET_ENDBR
#endif
.intel_syntax noprefix
.global blake3_hash_many_sse41... |
0vercl0k/wtf | 66,050 | src/libs/BLAKE3/c/blake3_avx2_x86-64_unix.S | #if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(__ELF__) && defined(__CET__) && defined(__has_include)
#if __has_include(<cet.h>)
#include <cet.h>
#endif
#endif
#if !defined(_CET_ENDBR)
#define _CET_ENDBR
#endif
.intel_syntax noprefix
.global _blake3_hash_many_avx2... |
0intro/9legacy | 4,084 | sys/src/9/teg2/arm.s | /*
* nvidia tegra 2 machine assist, definitions
* dual-core cortex-a9 processor
*
* R9 and R10 are used for `extern register' variables.
* R11 is used by the loader as a temporary, so avoid it.
*/
#include "mem.h"
#include "arm.h"
#undef B /* B is for 'botch' */
#define KADDR(pa) (KZERO | ((pa) & ~KSEGM... |
0vercl0k/wtf | 89,364 | src/libs/BLAKE3/c/blake3_avx512_x86-64_unix.S | #if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(__ELF__) && defined(__CET__) && defined(__has_include)
#if __has_include(<cet.h>)
#include <cet.h>
#endif
#endif
#if !defined(_CET_ENDBR)
#define _CET_ENDBR
#endif
.intel_syntax noprefix
.global _blake3_hash_many_avx5... |
0vercl0k/wtf | 66,736 | src/libs/BLAKE3/c/blake3_avx2_x86-64_windows_gnu.S | .intel_syntax noprefix
.global _blake3_hash_many_avx2
.global blake3_hash_many_avx2
.section .text
.p2align 6
_blake3_hash_many_avx2:
blake3_hash_many_avx2:
push r15
push r14
push r13
push r12
push rsi
push rdi
push rbx
push ... |
0vercl0k/wtf | 68,858 | src/libs/BLAKE3/c/blake3_sse2_x86-64_unix.S | #if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(__ELF__) && defined(__CET__) && defined(__has_include)
#if __has_include(<cet.h>)
#include <cet.h>
#endif
#endif
#if !defined(_CET_ENDBR)
#define _CET_ENDBR
#endif
.intel_syntax noprefix
.global blake3_hash_many_sse2
... |
0intro/9legacy | 8,905 | sys/src/9/teg2/lexception.s | /*
* arm exception handlers
*/
#include "arm.s"
#undef B /* B is for 'botch' */
/*
* exception vectors, copied by trapinit() to somewhere useful
*/
TEXT vectors(SB), 1, $-4
MOVW 0x18(R15), R15 /* reset */
MOVW 0x18(R15), R15 /* undefined instr. */
MOVW 0x18(R15), R15 /* SWI & SMC */
MOVW 0x18(R15), R1... |
0vercl0k/wtf | 63,460 | src/libs/BLAKE3/c/blake3_sse41_x86-64_windows_gnu.S | .intel_syntax noprefix
.global blake3_hash_many_sse41
.global _blake3_hash_many_sse41
.global blake3_compress_in_place_sse41
.global _blake3_compress_in_place_sse41
.global blake3_compress_xof_sse41
.global _blake3_compress_xof_sse41
.section .text
.p2align 6
_blake3_hash_many_sse41:
blake3_hash_many_sse41:
... |
0intro/9legacy | 4,750 | sys/src/9/teg2/rebootcode.s | /*
* arm v7 reboot code
*
* must fit in 11K to avoid stepping on PTEs; see mem.h.
* cache parameters are at CACHECONF.
*/
#include "arm.s"
/*
* All caches but L1 should be off before calling this.
* Turn off MMU, then copy the new kernel to its correct location
* in physical memory. Then jump to the start of ... |
0intro/9legacy | 28,847 | sys/src/9/vt5/l.s | /* virtex5 ppc440x5 machine assist */
#include "mem.h"
#define CPU0ONLY /* if defined, put cpu1 to sleep for now */
/*
* Special Purpose Registers of interest here (440 versions)
*/
#define SPR_CCR0 0x3b3 /* Core Configuration Register 0 */
#define SPR_CCR1 0x378 /* core configuration register 1 */
#define SPR_... |
0intro/9legacy | 1,729 | sys/src/9/vt5/tlb.s | /* virtex5 ppc440x5 initial tlb entries */
#include "mem.h"
#define MB (1024*1024)
/*
* TLB prototype entries, loaded once-for-all at startup,
* remaining unchanged thereafter.
* Limit the table size to ensure it fits in small TLBs.
*/
#define TLBE(hi, md, lo) WORD $(hi); WORD $(md); WORD $(lo)
/*
* ... |
0intro/9legacy | 4,340 | sys/src/9/vt5/rebootcode.s | /* virtex5 ppc440x5 reboot code */
#include "mem.h"
#define SPR_SRR0 26 /* Save/Restore Register 0 */
#define SPR_SRR1 27 /* Save/Restore Register 1 */
#define SPR_DBCR0 0x134 /* Debug Control Register 0 */
#define SPR_DBCR1 0x135 /* Debug Control Register 1 */
#define SPR_DBCR2 0x136 /* Debug Control Register 1 ... |
0intro/9legacy | 20,637 | sys/src/9/ppc/l.s | #include "mem.h"
/* use of SPRG registers in save/restore */
#define SAVER0 SPRG0
#define SAVER1 SPRG1
#define SAVELR SPRG2
#define SAVEXX SPRG3
#ifdef ucuconf
/* These only exist on the PPC 755: */
#define SAVER4 SPRG4
#define SAVER5 SPRG5
#define SAVER6 SPRG6
#define SAVER7 SPRG7
#endif /* ucuconf */
/* special in... |
0intro/9legacy | 10,996 | sys/src/9/mtx/l.s | #include "mem.h"
/* use of SPRG registers in save/restore */
#define SAVER0 SPRG0
#define SAVER1 SPRG1
#define SAVELR SPRG2
#define SAVEXX SPRG3
/* special instruction definitions */
#define BDNZ BC 16,0,
#define BDNE BC 0,2,
#define TLBIA WORD $((31<<26)|(307<<1))
#define TLBSYNC WORD $((31<<26)|(566<<1))
/* on so... |
0intro/9legacy | 1,476 | sys/src/9/mtx/inb.s | #include "mem.h"
#define BDNZ BC 16,0,
#define BDNE BC 0,2,
TEXT inb(SB), $0
OR $IOMEM, R3
MOVBZ (R3), R3
RETURN
TEXT insb(SB), $0
MOVW v+4(FP), R4
MOVW n+8(FP), R5
MOVW R5, CTR
OR $IOMEM, R3
SUB $1, R4
insb1:
MOVBZ (R3), R7
MOVBU R7, 1(R4)
BDNZ insb1
RETURN
TEXT outb(SB), $0
MOVW v+4(FP), R4
OR $IOME... |
0intro/9legacy | 20,780 | sys/src/9/loongson/l.s | #include "mem.h"
#include "spim.s"
/*
* entrypoint. set SB, pass arguments to main().
* PMON's calling convention:
* argc R4
* argv R5
* envp R6
* callvec R7
*/
TEXT start(SB), $-4
MOVW $setR30(SB), R30
PUTC('9', R1, R2)
/* don't enable any interrupts, out of EXL mode */
MOVW $CU1, R1
MOVW R1, M(STA... |
0intro/9legacy | 2,021 | sys/src/9/loongson/spim.s | #undef MASK
#define MASK(w) ((1<<(w))-1)
#define NOP NOR R0, R0, R0
#define CONST(x,r) MOVW $((x)&0xffff0000), r; OR $((x)&0xffff), r
#define LL(base, rt) WORD $((060<<26)|((base)<<21)|((rt)<<16))
#define SC(base, rt) WORD $((070<<26)|((base)<<21)|((rt)<<16))
#define ERET WORD $0x42000018; NOP
#define SYNC WORD $... |
0intro/9legacy | 1,493 | sys/src/9/pc/ptclbsum386.s | TEXT ptclbsum(SB), $0
MOVL addr+0(FP), SI
MOVL len+4(FP), CX
XORL AX, AX /* sum */
TESTL $1, SI /* byte aligned? */
MOVL SI, DI
JEQ _2align
DECL CX
JLT _return
MOVB 0x00(SI), AH
INCL SI
_2align:
TESTL $2, SI /* word aligned? */
JEQ _32loop
CMPL CX, $2 /* less than 2 bytes? */
JLT _1dreg
SUB... |
0intro/9legacy | 1,527 | sys/src/9/pc/apmjump.s | /*
* Far call, absolute indirect.
* The argument is the offset.
* We use a global structure for the jump params,
* so this is *not* reentrant or thread safe.
*/
#include "mem.h"
#define SSOVERRIDE BYTE $0x36
#define CSOVERRIDE BYTE $0x2E
#define RETF BYTE $0xCB
GLOBL apmjumpstruct+0(SB), $8
TEXT fortytwo(SB),... |
0intro/9legacy | 30,490 | sys/src/9/pc/l.s | #include "mem.h"
#include "/sys/src/boot/pc/x16.h"
#undef DELAY
#define PADDR(a) ((a) & ~KZERO)
#define KADDR(a) (KZERO|(a))
/*
* Some machine instructions not handled by 8[al].
*/
#define OP16 BYTE $0x66
#define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
#define CPUID BYTE $0x0F; BYTE $0xA2 /* CPUID, argument i... |
0intro/9legacy | 3,037 | sys/src/9/pc/apbootstrap.s | /*
* Start an Application Processor. This must be placed on a 4KB boundary
* somewhere in the 1st MB of conventional memory (APBOOTSTRAP). However,
* due to some shortcuts below it's restricted further to within the 1st
* 64KB. The AP starts in real-mode, with
* CS selector set to the startup memory address/16;
... |
0intro/9legacy | 3,281 | sys/src/9/bcm/l.s | /*
* Common startup and coprocessor instructions for armv6 and armv7
* The rest of l.s has been moved to armv[67].s
*/
#include "arm.s"
/*
* on bcm2836, only cpu0 starts here
* other cpus enter at cpureset in armv7.s
*/
TEXT _start(SB), 1, $-4
/*
* load physical base for SB addressing while mmu is off
* ke... |
0intro/9legacy | 5,160 | sys/src/9/bcm/cache.v7.s | /*
* cortex arm arch v7 cache flushing and invalidation
* shared by l.s and rebootcode.s
*/
#define BPIALL MCR CpSC, 0, R0, C(CpCACHE), C(5), 6 /* branch predictor invalidate all */
TEXT cacheiinv(SB), $-4 /* I invalidate */
DSB
MOVW $0, R0
MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall /* ok on cor... |
0intro/9legacy | 1,414 | sys/src/9/bcm/arm.s | /*
* armv6/v7 machine assist, definitions
*
* loader uses R11 as scratch.
*/
#include "mem.h"
#include "arm.h"
#define PADDR(va) (PHYSDRAM | ((va) & ~KSEGM))
#define L1X(va) (((((va))>>20) & 0x0fff)<<2)
/*
* new instructions
*/
#define ISB \
MOVW $0, R0; \
MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCA... |
0intro/9legacy | 10,991 | sys/src/9/bcm/armv7.s | /*
* Broadcom bcm2836 SoC, as used in Raspberry Pi 2
* 4 x Cortex-A7 processor (armv7)
*/
#include "arm.s"
#define CACHELINESZ 64
#define ICACHELINESZ 32
#undef DSB
#undef DMB
#undef ISB
#define DSB WORD $0xf57ff04f /* data synch. barrier; last f = SY */
#define DMB WORD $0xf57ff05f /* data mem. barrier; last f ... |
0intro/9legacy | 7,326 | sys/src/9/bcm/lexception.s | /*
* arm exception handlers
*/
#include "arm.s"
/*
* exception vectors, copied by trapinit() to somewhere useful
*/
TEXT vectors(SB), 1, $-4
MOVW 0x18(R15), R15 /* reset */
MOVW 0x18(R15), R15 /* undefined instr. */
MOVW 0x18(R15), R15 /* SWI & SMC */
MOVW 0x18(R15), R15 /* prefetch abort */
MOVW 0x18(R1... |
0intro/9legacy | 4,201 | sys/src/9/bcm/rebootcode.s | /*
* armv6/armv7 reboot code
*/
#include "arm.s"
#define PTEDRAM (Dom0|L1AP(Krw)|Section)
#define PTELPAE (1<<10|3<<8|1<<0) /* AF | ShareInner | Block */
#define WFI WORD $0xe320f003 /* wait for interrupt */
#define WFE WORD $0xe320f002 /* wait for event */
/*
* CPU0:
* main(PADDR(entry), PADDR(code), size);... |
0intro/9legacy | 6,169 | sys/src/9/bcm/armv6.s | /*
* Broadcom bcm2835 SoC, as used in Raspberry Pi
* arm1176jzf-s processor (armv6)
*/
#include "arm.s"
#define CACHELINESZ 32
TEXT armstart(SB), 1, $-4
/*
* SVC mode, interrupts disabled
*/
MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1
MOVW R1, CPSR
/*
* disable the mmu and L1 caches
* invalidate caches and ... |
0intro/9legacy | 1,130 | sys/src/libc/power/atom.s | TEXT ainc(SB),$0 /* long ainc(long *); */
MOVW R3, R4
xincloop:
LWAR (R4), R3
ADD $1, R3
DCBT (R4) /* fix 405 errata cpu_210 */
STWCCC R3, (R4)
BNE xincloop
RETURN
TEXT adec(SB),$0 /* long adec(long *); */
MOVW R3, R4
xdecloop:
LWAR (R4), R3
ADD $-1, R3
DCBT (R4) /* fix 405 errata cpu_210 */
STWCCC R... |
0intro/9legacy | 1,211 | sys/src/libc/power/memset.s | TEXT memset(SB),$0
#define BDNZ BC 16,0,
MOVW R3, p+0(FP) /* R3 is pointer */
/*
* performance:
* about 100mbytes/sec (8k blocks) on a 603/105 without L2 cache
* drops to 40mbytes/sec (10k blocks) and 28mbytes/sec with 32k blocks
*/
MOVW n+8(FP), R4 /* R4 is count */
CMP R4, $0
BLE ret
MOVW c+4(FP), R5 /... |
0intro/9legacy | 2,479 | sys/src/libc/power/memmove.s | #define BDNZ BC 16,0,
TEXT memmove(SB), $0
BR move
TEXT memcpy(SB), $0
move:
/*
* performance:
* (tba)
*/
MOVW R3, s1+0(FP)
MOVW n+8(FP), R9 /* R9 is count */
MOVW R3, R10 /* R10 is to-pointer */
CMP R9, $0
BEQ ret
BLT trap
MOVW s2+4(FP), R11 /* R11 is from-pointer */
/*
* if no more than 16 bytes... |
0intro/9legacy | 1,493 | sys/src/libc/power/memcmp.s | TEXT memcmp(SB), $0
#define BDNZ BC 16,0,
MOVW R3, s1+0(FP) /* R3 is pointer1 */
/*
* performance:
* 67mb/sec aligned; 16mb/sec unaligned
*/
MOVW n+8(FP), R4 /* R4 is count */
MOVW s2+4(FP), R5 /* R5 is pointer2 */
/*
* let LSW do the work for 4 characters or less; aligned and unaligned
*/
CMP R4, $0
B... |
0intro/9legacy | 3,748 | sys/src/libc/power/vlop.s | #define BDNZ BC 16,0,
/*
* 64/64 division adapted from powerpc compiler writer's handbook
*
* (R3:R4) = (R3:R4) / (R5:R6) (64b) = (64b / 64b)
* quo dvd dvs
*
* Remainder is left in R7:R8
*
* Code comment notation:
* msw = most-significant (high-order) word, i.e. bits 0..31
* lsw = least-significant (low-orde... |
0intro/9legacy | 1,279 | sys/src/libc/386/atom.s | TEXT ainc(SB), $0 /* long ainc(long *); */
MOVL addr+0(FP), BX
ainclp:
MOVL (BX), AX
MOVL AX, CX
INCL CX
LOCK
BYTE $0x0F; BYTE $0xB1; BYTE $0x0B /* CMPXCHGL CX, (BX) */
JNZ ainclp
MOVL CX, AX
RET
TEXT adec(SB), $0 /* long adec(long*); */
MOVL addr+0(FP), BX
adeclp:
MOVL (BX), AX
MOVL AX, CX
DECL CX
LOCK
... |
0intro/9legacy | 1,250 | sys/src/libc/386/vlop.s | TEXT _mulv(SB), $0
MOVL r+0(FP), CX
MOVL a+4(FP), AX
MULL b+12(FP)
MOVL AX, 0(CX)
MOVL DX, BX
MOVL a+4(FP), AX
MULL b+16(FP)
ADDL AX, BX
MOVL a+8(FP), AX
MULL b+12(FP)
ADDL AX, BX
MOVL BX, 4(CX)
RET
/*
* _mul64by32(uint64 *r, uint64 a, uint32 b)
* sets *r = low 64 bits of 96-bit product a*b; returns hig... |
0intro/9legacy | 1,282 | sys/src/libc/sparc/memset.s | TEXT memset(SB),$0
/*
* performance:
* (tba)
*/
MOVW R7, 0(FP)
MOVW n+8(FP), R9 /* R9 is count */
MOVW p+0(FP), R10 /* R10 is pointer */
MOVW c+4(FP), R11 /* R11 is char */
ADD R9,R10, R12 /* R12 is end pointer */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to guarantee any
* rou... |
0intro/9legacy | 2,282 | sys/src/libc/sparc/memmove.s | TEXT memmove(SB), $0
JMP move
TEXT memcpy(SB), $0
move:
/*
* performance:
* (tba)
*/
MOVW R7, s1+0(FP)
MOVW n+8(FP), R9 /* R9 is count */
MOVW R7, R10 /* R10 is to-pointer */
SUBCC R0,R9, R0
BGE ok
MOVW 0(R0), R0
ok:
MOVW s2+4(FP), R11 /* R11 is from-pointer */
ADD R9,R11, R13 /* R13 is end from-... |
0intro/9legacy | 1,705 | sys/src/libc/sparc/memcmp.s | TEXT memcmp(SB), $0
/*
* performance:
* (tba)
*/
MOVW R7, 0(FP)
MOVW n+8(FP), R9 /* R9 is count */
MOVW s1+0(FP), R10 /* R10 is pointer1 */
MOVW s2+4(FP), R11 /* R11 is pointer2 */
ADD R9,R10, R12 /* R12 is end pointer1 */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to guarantee ... |
0intro/9legacy | 1,115 | sys/src/libc/sparc/strcpy.s | TEXT strcpy(SB), $0
MOVW R7, 0(FP)
MOVW s1+0(FP), R9 /* R9 is to pointer */
MOVW s2+4(FP), R10 /* R10 is from pointer */
/*
* test if both pointers
* are similarly word aligned
*/
XOR R9,R10, R7
ANDCC $3,R7, R0
BNE una
/*
* make byte masks
*/
MOVW $0xff, R17
SLL $8,R17, R16
SLL $16,R17, R13
SLL $24,... |
0intro/9legacy | 5,379 | sys/src/libc/sparc/muldivrt.s | /*
* ulong
* _udiv(ulong num, ulong den)
* {
* int i;
* ulong quo;
*
* if(den == 0)
* *(ulong*)-1 = 0;
* quo = num;
* if(quo > 1<<(32-1))
* quo = 1<<(32-1);
* for(i=0; den<quo; i++)
* den <<= 1;
* quo = 0;
* for(; i>=0; i--) {
* quo <<= 1;
* if(num >= den) {
* num -= den;
* qu... |
0intro/9legacy | 2,423 | sys/src/libc/sparc/vlop.s | TEXT _mulv(SB), $0
MOVW u1+8(FP), R8
MOVW u2+16(FP), R13
MOVW R13, R16 /* save low parts for later */
MOVW R8, R12
/*
* unsigned 32x32 => 64 multiply
*/
CMP R13, R8
BLE mul1
MOVW R12, R13
MOVW R16, R8
mul1:
MOVW R13, Y
ANDNCC $0xFFF, R13, R0
BE mul_shortway
ANDCC R0, R0, R9 /* zero partial product ... |
0intro/9legacy | 1,953 | sys/src/libc/riscv64/atom.s | /*
* RISC-V atomic operations
* assumes A extension
* LR/SC only work on cached regions
*/
#define ARG 8
#define MASK(w) ((1<<(w))-1)
#define FENCE WORD $(0xf | MASK(8)<<20) /* all i/o, mem ops before & after */
#define AQ (1<<26) /* acquire */
#define RL (1<<25) /* release */
#define LRW(rs1, rd) \
WORD $(... |
0intro/9legacy | 1,304 | sys/src/libc/riscv64/memset.s | TEXT memset(SB),$12
MOV R8, s1+0(FP)
MOV R8, R11 /* R11 is pointer */
MOVWU c+8(FP), R12 /* R12 is char */
MOVWU n+12(FP), R10 /* R10 is count */
ADD R10,R11, R13 /* R13 is end pointer */
/*
* if not at least 8 chars,
* dont even mess around.
* 7 chars to guarantee any
* rounding up to a doubleword
* ... |
0intro/9legacy | 1,592 | sys/src/libc/riscv/atom.s | /*
* RISC-V atomic operations
* assumes A extension
*/
#define LINK R1
#define SP R2
#define ARG 8
#define SYNC WORD $0xf /* FENCE */
#define LRW(rs2, rs1, rd) \
WORD $((2<<27)|( 0<<20)|((rs1)<<15)|(2<<12)|((rd)<<7)|057)
#define SCW(rs2, rs1, rd) \
WORD $((3<<27)|((rs2)<<20)|((rs1)<<15)|(2<<12)|((rd)<<7)|057)... |
0intro/9legacy | 1,258 | sys/src/libc/riscv/memset.s | TEXT memset(SB),$12
MOVW R8, s1+0(FP)
MOVW n+8(FP), R10 /* R10 is count */
MOVW p+0(FP), R11 /* R11 is pointer */
MOVW c+4(FP), R12 /* R12 is char */
ADD R10,R11, R13 /* R13 is end pointer */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to guarantee any
* rounding up to a word
* boun... |
0intro/9legacy | 1,888 | sys/src/libc/riscv/memmove.s |
TEXT memcpy(SB), $-4
TEXT memmove(SB), $-4
MOVW R8, s1+0(FP)
MOVW n+8(FP), R9 /* count */
BEQ R9, return
BGT R9, ok
MOVW $0, R9
ok:
MOVW s1+0(FP), R11 /* dest pointer */
MOVW s2+4(FP), R10 /* source pointer */
BLTU R11, R10, back
/*
* byte-at-a-time forward copy to
* get source (R10) aligned.
*/
f1:
A... |
0intro/9legacy | 1,688 | sys/src/libc/riscv/memcmp.s | TEXT memcmp(SB), $0
MOVW R8, s1+0(FP)
MOVW n+8(FP), R15 /* R15 is count */
MOVW s1+0(FP), R9 /* R9 is pointer1 */
MOVW s2+4(FP), R10 /* R10 is pointer2 */
ADD R15,R9, R11 /* R11 is end pointer1 */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to guarantee any
* rounding up to a word
... |
0intro/9legacy | 1,250 | sys/src/libc/riscv/strcpy.s | TEXT strcpy(SB), $0
MOVW s2+4(FP),R9 /* R9 is from pointer */
MOVW R8, R10 /* R10 is to pointer */
/*
* align 'from' pointer
*/
l1:
AND $3, R9, R12
ADD $1, R9
BEQ R12, l2
MOVB -1(R9), R12
ADD $1, R10
MOVB R12, -1(R10)
BNE R12, l1
RET
/*
* test if 'to' is also aligned
*/
l2:
AND $3,R10, R12
BEQ R12... |
0intro/9legacy | 1,411 | sys/src/libc/arm/atom.s | #define DMB MCR 15, 0, R0, C7, C10, 5
#define CLREX WORD $0xf57ff01f
#define LDREX(a,r) WORD $(0xe<<28|0x01900f9f | (a)<<16 | (r)<<12)
/* `The order of operands is from left to right in dataflow order' - asm man */
#define STREX(v,a,r) WORD $(0xe<<28|0x01800f90 | (a)<<16 | (r)<<12 | (v)<<0)
/*
* int cas(ulong *p, ul... |
0intro/9legacy | 4,196 | sys/src/libc/arm/memmove.s | TS = 0
TE = 1
FROM = 2
N = 3
TMP = 3 /* N and TMP don't overlap */
TMP1 = 4
TEXT memcpy(SB), $0
B _memmove
TEXT memmove(SB), $0
_memmove:
MOVW R(TS), to+0(FP) /* need to save for return value */
MOVW from+4(FP), R(FROM)
MOVW n+8(FP), R(N)
ADD R(N), R(TS), R(TE) /* to end pointer */
CMP R(FROM), R(TS)
BLS... |
0intro/9legacy | 1,639 | sys/src/libc/arm/div.s | Q = 0
N = 1
D = 2
CC = 3
TMP = 11
TEXT save<>(SB), 1, $0
MOVW R(Q), 0(FP)
MOVW R(N), 4(FP)
MOVW R(D), 8(FP)
MOVW R(CC), 12(FP)
MOVW R(TMP), R(Q) /* numerator */
MOVW 20(FP), R(D) /* denominator */
CMP $0, R(D)
BNE s1
MOVW -1(R(D)), R(TMP) /* divide by zero fault */
s1: RET
TEXT rest<>(SB), 1, $0
MOVW 0(F... |
0intro/9legacy | 1,278 | sys/src/libc/spim64/memset.s | TEXT memset(SB), $0
MOVV R1, 0(FP)
/*
* performance:
* about 1us/call and 28mb/sec
*/
MOVW n+16(FP), R3 /* R3 is count */
MOVV p+0(FP), R4 /* R4 is pointer */
MOVW c+8(FP), R5 /* R5 is char */
ADDVU R3,R4, R6 /* R6 is end pointer */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to g... |
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